1. Field of the Invention
This invention relates to a computer and, more particularly, to a bus interface unit which allows a peripheral device to read data from a local memory in sequential address order by rearranging bits within the initial address forwarded to the local memory and de-queuing data until an initial target data is aligned for transfer to the peripheral device. Subsequent transfer cycles occur in address order to complete a cache line, and subsequent cache lines are transferred at cache line boundaries until the entire transfer operation is complete.
2. Description of the Related Art
Modern computers are called upon to execute instructions and transfer data at increasingly higher rates. Many computers employ CPUs which operate at clocking rates exceeding several hundred MHz, and further have multiple buses connected between the CPUs and numerous input/output devices. The buses may have dissimilar protocols depending on which devices they link. For example, a CPU local bus connected directly to the CPU preferably transfers data at a faster rate than a peripheral bus connected to slower input/output devices. A mezzanine bus may be used to connect devices arranged between the CPU local bus and the peripheral bus. The peripheral bus can be classified as, for example, an industry standard architecture ("ISA") bus, an enhanced ISA ("EISA") bus or a microchannel bus. The mezzanine bus can be classified as, for example, a peripheral component interconnect ("PCI") bus to which higher speed input/output devices can be connected.
Coupled between the various buses are bus interface units. According to somewhat known terminology, the bus interface unit coupled between the CPU bus and the PCI bus is often termed the "north bridge". Similarly, the bus interface unit between the PCI bus and the peripheral bus is often termed the "south bridge".
The north bridge, henceforth termed a bus interface unit, serves to link specific buses within the hierarchical bus architecture. Preferably, the bus interface unit couples data, address and control signals forwarded between the CPU local bus, the PCI bus and the memory bus. Accordingly, the bus interface unit may include various buffers and/or controllers situated at the interface of each bus linked by the interface unit. In addition, the bus interface unit may receive data from a dedicated graphics bus, and therefore may include an advanced graphics port ("AGP") and/or a graphic component interface ("GCI") at the interface to that bus.
Mastership of the various buses is preferably orchestrated by an arbiter within the bus interface unit. For example, if a peripheral input/output device coupled to the PCI bus or a dedicated graphics bus wishes to read data from local memory, it must solicit mastership of the PCI or graphics bus before doing so. Once mastership is granted, the peripheral device can then read the appropriate data from the local or system memory to temporary storage devices or "queues" within the bus interface unit.
Typically, data is arranged within the system memory according to cache lines. A read operation from system memory to the peripheral device of a cache line generally involves several clock cycles. For example, a cache line may contain four quad words and each read cycle can transfer one quad word or eight bytes across a 64-bit memory bus.
A particular byte within the cache line can therefore be addressed by several bits. The least significant three bits can be used to determine a particular offset within each quad word, and the next two least significant bits are used to determine which quad word is being addressed within the cache line.
In many instances in which a peripheral device requests data from system memory, the first address dispatched to the memory controller designates either the first, second, third or fourth quad word within a particular cache line. Thus, it is said that the initial address is not constrained to a cache line boundary. Unless a particular addressing mode is used to extract quad words from a cache line, the memory controller will typically dispatch quad words according to the well known "toggle mode".
Toggle mode addressing of a cache line is generally known as the standard mechanism by which a microprocessor will extract data. Generally speaking, the order by which data is read from system memory depends on which quad word is first addressed. The first-addressed quad word is often referred to as the "target" quad word. Toggle mode addressing can be thought of as dividing a cache line in half, wherein the next successive quad word is dependent on where in the cache line the target quad word resides. For example, if the target quad word resides at hexadecimal address location 08 (or 01000 binary), then the target quad word will be read first, followed by quad word at address 00 to complete the ordering of the first half of the cache line being read. The second half of the cache line is read identical to the first half. That is, the quad word at hexadecimal address location 18 will be read before address location 10.
The mechanism of toggle mode addressing from an initial target address until the entire cache line is transferred is generally well known as a conventional microprocessor addressing. Unfortunately, a peripheral device connected to the PCI bus or the AGP/GCI graphics bus wants bursts of data in sequential addressing order (i.e., data which reside at addresses having numerically increasing values). In particular, a peripheral device generally reads data beginning at a target address and thereafter desires a quad word addressed by a next successive address location. For example, a peripheral device requires that the data be read to that device beginning with the least significant 5 bit address (e.g., hexadecimal 00, then 08, then 10, and then 18). Once the initial cache line has been read by the peripheral device, the next successive address generally aligns at the cache line boundary so that all subsequent quad words are addressed in proper sequential order. However, the target address for the first cache line to be read by the peripheral device must somehow be modified so that a sequential order of quad words can be sent to the peripheral device rather than quad words sent in toggle mode.
It would therefore be beneficial to derive a bus interface unit which can modify the target address to that of an initial address used to read the first (lowest addressable) quad word within a sequence of quad words forming the cache line. By modifying the addressing seen by the memory controller, the initial cache line is extracted in an order conducive to a peripheral device reading that cache line. However, quad words sent to the peripheral device before the target-address quad words must somehow be kept track of and properly discarded.